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MAX15070A/MAX15070B
7A Sink, 3A Source,
12ns, SOT23 MOSFET Drivers
IN+
V IH
V IL
P_OUT AND
N_OUT
CONNECTED
90%
TOGETHER
10%
t D-OFF
t F
t D-ON
t R
TIMING DIAGRAM
V+
V+
MAX15070A
MAX15070B
INPUT
IN+
P_OUT
IN-
GND
N_OUT
C L
OUTPUT
TEST CIRCUIT
Figure 1. Timing Diagram and Test Circuit
Detailed Description
Logic Inputs
The MAX15070A/MAX15070Bs’ logic inputs are pro-
tected against voltage spikes up to +16V, regardless of
the V+ voltage. The low 10pF input capacitance of the
inputs reduces loading and increases switching speed.
These ICs have two inputs that give the user greater
flexibility in controlling the MOSFET. Table 1 shows all
possible input combinations. The difference between the
MAX15070A and the MAX15070B is the input threshold
voltage. The MAX15070A has TTL logic-level thresholds,
while the MAX15070B has HNM (CMOS-like) logic-level
thresholds (see the Electrical Characteristics ). Connect
IN+ to V+ or IN- to GND when not used. Alternatively,
the unused input can be used as an on/off control input
(Table 1).
Undervoltage Lockout (UVLO)
When V+ is below the UVLO threshold, the n-channel is
on and the p-channel is off, independent of the state of
the inputs. The UVLO is typically 3.45V with 200mV typi-
cal hysteresis to avoid chattering. A typical falling delay
of 2 F s makes the UVLO immune to narrow negative tran-
sients in noisy environments.
Table 1. Truth Table
IN+ IN- p-CHANNEL
L L Off
L H Off
H L On
H H Off
L = Logic-low, H = Logic-high.
Maxim Integrated
n-CHANNEL
On
On
Off
On
Driver Outputs
The ICs provide two separate outputs. One is an open-
drain p-channel, the other an open-drain n-channel. They
have distinct current sourcing/sinking capabilities to inde-
pendently control the rise and fall times of the MOSFET
gate. Add a resistor in series with P_OUT/N_OUT to slow
the corresponding rise/fall time of the MOSFET gate.
7
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